The present invention generally relates to Built-in-self repair (BISR) designs, and more specifically relates to a BISR design which is configured to test redundant elements and regular functional memory to avoid test escapes.
BISR detects and repairs defects in memories. Testing of redundant locations is an important aspect of the BISR algorithm. It is not always very easy to test redundant locations completely.
A current solution is to bitmap all the failures and post-process it to determine whether or not the failure is related to defects in redundant locations. However, it is almost impossible to bitmap all failing memories in the production flow. This significantly impacts tester time and increases cost. Another current solution is to check the unused redundant elements along with the functional space next to them via BIST. However, using BIST to test limited addresses results in a very complicated algorithm, increases gate count and can potentially impact yield.
Huang et al. had proposed a method to test the redundant elements along with regular memory in U.S. Pat. No. 6,640,321. U.S. Pat. No. 6,640,321 is hereby incorporated herein by reference in its entirety. The method proposed in that patent is useful for memories which employ only redundant rows. The basic idea is to generate Built-in-self-test (BIST) with additional words (more than the actual functional space) and use the additional words access to access the redundant elements during BIST run. The method requires complicated masking of false failure during Built-in-self-repair (BISR) and BIST runs. These failures occur because BIST tries to test more words then existing in the functional space all the time. Moreover, it becomes very complicated if we have both redundant rows and redundant columns. It also requires special design in the memory to support this method.
In another method, redundant elements are remapped to repair the defective elements on the fly as soon as the defective elements are assessed. BIST run is then re-started from where it was stopped. This requires special BIST design and handling and will be impossible to achieve with third party BIST designs. Moreover, it is almost impossible to assess the replacement of defects with either row or column (in case of row and column redundancy) since the actual assignments of redundant rows or columns are done at the end. This method still has potential test escapes because of not getting proper background physical patterns.